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Multi-core Processors
Year started2014
Latest versionA
November 2016 (2016-11)

CAST-32A, Multi-core Processors is a position paper,[1] by the Certification Authorities Software Team (CAST). It is not official guidance, but is considered informational by certification authorities such as the FAA and EASA. A key point is that Multi-core processor "interference can affect execution timing behavior, including worst case execution time (WCET)."[2]

The original document was published in 2014 by an "international group of certification and regulatory authority representatives."[3] The current revision A was released in 2016. "The Federal Aviation Administration (FAA) and European Aviation Safety Agency (EASA) worked with industry to quantify a set of requirements and guidance that should be met to certify and use multi-core processors in civil aviation, described e.g. in the FAA CAST-32A Position Paper and the EASA Use of MULticore proCessORs in airborne Systems (MULCORS) research report."[4] For applicants certifying under EASA, AMC 20-193 has now superseded CAST-32A since it AMC20-193 release on 21 January 2022. It is expected that the FAA will release its Advisory Circular AC 20-193 guidance in 2022, which is expected to be almost identical to AMC 20-193. [5][6]

One of the first mixed-criticality multicore avionics systems is expected to be certified sometime in 2020.[7] The objectives of the standard are applicable to software on multicore processors, including the operating system.[8][9] However, the nature of the underlying processor hardware must examined in detail to identify potential interference channels due to inter-core contention for shared resources.[10] Verification that multicore interference channels have been mitigated can be accomplished through the use of interference generators, i.e., software tuned to create a heavy usage pattern on a shared resource.[11] By creating stress on the shared resource, the impact of contention between cores can be measured and quantified.[12]


The standard presents nine objectives that must be met for Design Assurance Level (DAL) A or B. Six of the objectives apply for DAL C. The standard does not apply for DAL D or E. [1]

Objective Applicable Design Assurance Levels
MCP Planning 1 A, B, C
MCP Resource Usage 1 A, B, C
MCP Resource Usage 2 A, B
MCP Planning 2 A, B, C
MCP Resource Usage 3 A, B
MCP Resource Usage 4 A, B
MCP Software 1 A, B, C
MCP Software 2 A, B, C
MCP Error Handling 1 A, B
MCP Accomplishment Summary 1 A, B, C


  1. ^ a b "Multi-core Processors" (PDF). CAST-32A. Federal Aviation Administration. 1 November 2016. Retrieved 23 March 2020.
  2. ^ VanderLeest, Steven H.; Evripidou, Christos (10 March 2020). "An Approach to Verification of Interference Concerns for Multicore Systems (CAST-32A)". SAE Technical Paper Series. Vol. 1. SAE International. pp. 1174–1181. doi:10.4271/2020-01-0016. S2CID 213352079. Retrieved 11 March 2020.
  3. ^ Kühlert, Oliver (11 February 2020). "Multi-Core Ready to Become Airborne". Embedded Computing Design.
  4. ^ Athavale, Jyotika; Mariani, Riccardo; Paulitsch, Michael (19 March 2019). "Flight Safety Certification Implications for Complex Multi-Core Processor Based Avionics Systems". 2019 IEEE International Reliability Physics Symposium (IRPS). IEEE: 1–6. doi:10.1109/IRPS.2019.8720422. ISBN 978-1-5386-9504-3. S2CID 169037813.
  5. ^ Wolfe, Frank (28 February 2020). "EASA and FAA to Issue Further Guidance on Multicore Certification This Year". Avionics International. Retrieved 9 March 2020.
  6. ^ "Certification Authorities Software Team (CAST)". Federal Aviation Administration. Retrieved 29 October 2021.
  7. ^ Radack, David; Tiedeman, Jr., Harold G.; Parkinson, Paul (2018). "Civil Certification of Multi-core Processing Systems in Commercial Avionics". Rockwell Collins. Retrieved 23 March 2020.
  8. ^ "DDC-I and Rapita Systems Simplify Verification and Certification of Multicore Avionics Applications". 21 April 2020. Retrieved 23 March 2020.
  9. ^ Brown, Mark (15 November 2018). "CAST=32A: Significance and Implications". Retrieved 11 December 2020.
  10. ^ Agirre, Irune; Abella, Jaume; Azkarate-askasua, Mikel; Cazorla, Francisco (14 June 2017). "On the Tailoring of CAST-32A CertificationGuidance to Real COTS Multicore Architectures". IEEE. Retrieved 23 March 2020.
  11. ^ VanderLeest, Steven H.; Evripidou, Christos (10 March 2020). "An Approach to Verification of Interference Concerns for Multicore Systems". SAE International Journal of Advances and Current Practices in Mobility. SAE. 2 (3): 1174–1181. doi:10.4271/2020-01-0016. S2CID 213352079. Retrieved 23 March 2020.
  12. ^ Wright, Daniel (10 November 2019). "Multicore Timing Analysis for DO-178C". Rapita systems. Retrieved 17 January 2022.