This article may be too technical for most readers to understand.(August 2021)
CAST-32A, Multi-core Processors is a position paper, by the Certification Authorities Software Team (CAST). It is not official guidance, but is considered informational by certification authorities such as the FAA and EASA. A key point is that Multi-core processor "interference can affect execution timing behavior, including worst case execution time (WCET)."
The original document was published in 2014 by an "international group of certification and regulatory authority representatives." The current revision A was released in 2016. "The Federal Aviation Administration (FAA) and European Aviation Safety Agency (EASA) worked with industry to quantify a set of requirements and guidance that should be met to certify and use multi-core processors in civil aviation, described e.g. in the FAA CAST-32A Position Paper and the EASA Use of MULticore proCessORs in airborne Systems (MULCORS) research report." For applicants certifying under EASA, AMC 20-193 has now superseded CAST-32A since it AMC20-193 release on 21 January 2022. It is expected that the FAA will release its Advisory Circular AC 20-193 guidance in 2022, which is expected to be almost identical to AMC 20-193. 
One of the first mixed-criticality multicore avionics systems is expected to be certified sometime in 2020. The objectives of the standard are applicable to software on multicore processors, including the operating system. However, the nature of the underlying processor hardware must examined in detail to identify potential interference channels due to inter-core contention for shared resources. Verification that multicore interference channels have been mitigated can be accomplished through the use of interference generators, i.e., software tuned to create a heavy usage pattern on a shared resource. By creating stress on the shared resource, the impact of contention between cores can be measured and quantified.
|Objective||Applicable Design Assurance Levels|
|MCP Planning 1||A, B, C|
|MCP Resource Usage 1||A, B, C|
|MCP Resource Usage 2||A, B|
|MCP Planning 2||A, B, C|
|MCP Resource Usage 3||A, B|
|MCP Resource Usage 4||A, B|
|MCP Software 1||A, B, C|
|MCP Software 2||A, B, C|
|MCP Error Handling 1||A, B|
|MCP Accomplishment Summary 1||A, B, C|
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- "Certification Authorities Software Team (CAST)". Federal Aviation Administration. Retrieved 29 October 2021.
- Radack, David; Tiedeman, Jr., Harold G.; Parkinson, Paul (2018). "Civil Certification of Multi-core Processing Systems in Commercial Avionics". Rockwell Collins. Retrieved 23 March 2020.
- "DDC-I and Rapita Systems Simplify Verification and Certification of Multicore Avionics Applications". 21 April 2020. Retrieved 23 March 2020.
- Brown, Mark (15 November 2018). "CAST=32A: Significance and Implications". Retrieved 11 December 2020.
- Agirre, Irune; Abella, Jaume; Azkarate-askasua, Mikel; Cazorla, Francisco (14 June 2017). "On the Tailoring of CAST-32A CertificationGuidance to Real COTS Multicore Architectures". IEEE. Retrieved 23 March 2020.
- VanderLeest, Steven H.; Evripidou, Christos (10 March 2020). "An Approach to Verification of Interference Concerns for Multicore Systems". SAE International Journal of Advances and Current Practices in Mobility. SAE. 2 (3): 1174–1181. doi:10.4271/2020-01-0016. S2CID 213352079. Retrieved 23 March 2020.
- Wright, Daniel (10 November 2019). "Multicore Timing Analysis for DO-178C". Rapita systems. Retrieved 17 January 2022.